EECS 312 lecture01.intro

Digital Integrated Circuits

Introduction

Whoami: David Garmire, dgarmire@umich.edu, - Please reach out anytime with questions!
I prefer to talk over Zoom: https://umich.zoom.us/my/dgarmire

Outline

Logistics
Coverage
Background
Rapid Overview
Review of Key Concepts

Digital Integrated Circuits

Why digital?
Robust to conditions, easy to manipulate, repeatable, scalable
Computation methods available:
Compression, encryption, digital signal processing, digital control
Why integrated?
Smaller, lower power, cost less, more functionality
Integrate GPU / WiFi / cache / memory controllers

Intel Core Ultra (Meteor/Lunar Lake class):
Disaggregated tiles with Foveros 3D packaging
Heterogeneous nodes (Intel + TSMC, 3-4 nm class)
Integrated NPU for on-device AI; PCIe 5 + DDR5/LPDDR5X

AMD Ryzen AI 300 (Zen 5):
Zen 5 CPU + RDNA GPU + XDNA NPU
Chiplet ecosystem; 3D V-Cache options in desktop/server
Advanced 4 nm class silicon

Apple M4:
3 nm class SoC with unified memory
Powerful GPU + Neural Engine
Tight HW/SW integration across Apple platforms

Sources: source 1 source 2 source 3

Digital Integrated Circuits

Explosion of possibility
IOT: 2030E market size ~= $0.87T
GPU (data center): 2030E market size ~= $228B
AI chip: 2030E market size ~= $194B
Mobile/smartphone: 2030E market size ~= $530B

Estimated projection only

Sources: iot gpu ai mobile

What is this class all about?

Transistor-level digital integrated circuit
Device physics
Design principles and layout
Models and simulation
Verification
Models allow us to reason about circuit behavior
Analyze and optimize circuit performance:
Power, cost, performance.
Teach you how to make sure your circuit works/performs
Do you want your transistor to be the one that renders a 1 billion transistor chip useless?

Topics

Complementary Metal Oxide (CMOS) devices
Manufacturing Technology
Gates
Digital Circuits
Inverters
Combinational and sequential logic
Propagation delay
Reliability
Power
Interconnects
Modeling and representation
Memories

Design Abstraction Levels

System: e.g., Processor
Module: e.g., MUX
Gate: e.g., NAND
Circuit: e.g., inverter
Device: e.g., transistor layers

Class Organization, Style

Before class: read material
Class: Interactive lecture and/or problems
Participation is important
Lab assignment: Individual, guide-like
Need to sign NDA
Design project: Group of 2/3
Exams: Online midterm and final
Examine your self improvement, proficiency

Some Important Announcements

Course messaging via Canvas announcements and email
Use email for private questions or exam questions
Use office hours or in-class Q&A for general questions
You are encouraged to work together on your homework and lab assignments
But you must turn in your own solution based on your understanding
You must not copy each others’ assignments
Engineering Honor Code

Class Style

Active learning drives retention: discussion, practice, and teaching others matter.
We will mix short lecture segments with demos, problems, and peer discussion.
Students learn differently (visual/spatial, logical, verbal, interpersonal, etc.).
The course balances learning styles: sensory/intuitive, visual/verbal, active/reflective, sequential/global.
Ask questions in class; use office hours or email for follow-ups.

Sources: learning pyramid multiple intelligences Felder & Silverman (1988)

Class Material

Textbook: “Digital Integrated Circuits – A Design Perspective”, 2nd Edition, by J. Rabaey, A. Chandrakasan, B. Nikolic
Reading assignments will be given for each lecture
Assignments will be posted on canvas

Software

Cadence
Widely used in industry
Online tutorials and documents
SPICE for simulation
pyspice with ngspice
xyce (Sandia National Labs, possibly harder to install)

The First Computer

Babbage Difference Engine
Year: 1832
# Parts: 25,000
Cost: ~$2.5M (today)

Babbage Difference Engine

ENIAC - The first electronic computer (1946)

The Transistor Revolution

First transistor (point-contact)
John Bardeen and Walter Brattain
Bell Labs, 1947
Nobel Prize in Physics (1956)
William Shockley, John Bardeen, Walter Brattain
For their research on semiconductors and the discovery of the transistor effect

Bardeen and Brattain with early transistor apparatus

First Transistor Showing Scale

The First Integrated Circuit

Jack Kilby (Texas Instruments, 1958)

“a body of semiconductor material ... wherein all the components of the electronic circuit are completely integrated”

Nobel Prize in Physics (2000)
Jack Kilby (1/2) – the invention of the integrated circuit

First IC (showing scale)

First Commercially Successful Computer

IBM System/360 (1964)
First truly compatible family of mainframes across performance tiers
Standardized 8-bit byte, ISA, and I/O ecosystem
Massive investment (~$5B) paid off with rapid adoption
By 1969, IBM was shipping >1,000 System/360 systems/month
DEC PDP-8 (1965)
First commercially successful minicomputer
Low price (~$18,500) and compact size opened new markets
50,000+ units sold

Sources: System/360 investment System/360 shipments PDP-8

Intel 4004 Micro-Processor

1971
2,300 transistors
10um technology
~3 mm x 4 mm
108 KHz operation
Same computing power as ENIAC

Intel Pentium 4 Microprocessor

2000
42,000,000 transistors
0.18um technology
1.5 GHz operation

Intel Nehalem Microprocessor (2009)

731,000,000 transistors
3.6 GHz frequency
45nm technology
4 cores, 8 MB cache

Icelake Microprocessor (2019)

Process: 65nm LP CMOS
Size: 11.44x10.75 mm
Supply voltage: 1.2V
Freq: 3.6 GHz+ (CPU)
Power: 28 W TDP

Raptor Lake (2022)

Raptor cove and gracemont cores

Raptor Lake Refresh vs AMD Ryzen 9000

AMD Ryzen 9 9950X (Zen 5) vs Intel Core i9-14900K (Raptor Lake Refresh)
	AMD Ryzen 9 9950X	Intel Core i9-14900K
Release Date	Aug 15, 2024	Oct 17, 2023
Node / Design	4 nm	Intel 7 (10 nm)
Cores / Threads	16 Cores / 32 Threads	8P + 16E \| 24 Cores / 32 Threads
Peak Clocks	Up to 5.7 GHz	Up to 6.0 GHz
TDP / PBP / MTP	170W TDP	125W PBP / 253W MTP (TDP 125W)
Memory	DDR5	DDR4-3200 / DDR5-5600
PCIe	PCIe 5.0 - 24 lanes (CPU)	PCIe 5.0 - 16 lanes (CPU)

TDP: thermal design power. PBP: processor base power. MTP: max turbo power (Intel).

Sources: AMD 9950X Intel 14900K

Apple M2 (from Wikipedia)

Again specialization is occurring
4 (performance)+4 (energy efficient)
5nm (TSMC)
20+ Billion transistors
GPU on-chip
Dedicated neural network chip: 16-core
15.8 trillion operations

A Cell Phone Media Application Processor Chip (2009)

Process: 65nm LP CMOS
Size: 6.4x6.5 mm
Supply voltage: 1.2V
Freq: 500MHz (CPU)
166MHz (IPs)
Power: 342mW H.264 dec
443mW H.264 enc

Courtesy, Renesas

Apple A17 Pro (3nm), Qualcomm Snapdragon 8 Gen 3 (4nm), Samsung Exynos 2400 (4nm)

MediaTek Dimensity 9300 plus
Current leader (Taiwanese company)
Depending how you measure
Released in China, Vivo and Xiaomi
Generative AI support
Numerous comparison sites, but note:
Specialization allows some processors to be better at specific tasks: e.g., gaming or low power.
8+ cores, but specializing now as well
Heavy AI core development
12B+ transistors

“Ostrich” effect

Don’t fall for it

Sources: source

Markets

427 Stuff – Lookahead at possibilities

Process: 65nm CMOS
Supply voltage under 1.2V
Freq above 333 MHz
Design of layout and floorplan to optimize for area and speed, for the most part

Mobile Internet of Things

Moore’s Law

Gordon Moore (1965): transistor counts double about every 1–2 years
Revised to ~2 years by 1975
Where it slowed
~2005: Dennard scaling ended; clock rates stopped rising quickly
2010s–2020s: doubling slowed to ~2.5–3+ years; costs rose sharply
Progress continues via chiplets, 3D stacking, and specialization

Sources: Moore’s law Dennard scaling transistor counts

Moore's law plot with updated transistor counts (1971-2024)

Transistor Counts (Historical)

Transistor Counts (Recent)

Recent transistor counts by vendor (2010-2024, log10 scale)

Moore’s Law Changes

Upper limit on speed caused changes
Now more cores
Hybrid cores (performance vs energy efficient)
Continue to scale down sizes
Just now increasing speeds up above 5 GHz

Sources: source

Growth Rate

53% compound annual growth over 50 years
No other technology has grown so fast so long
Driven by miniaturization of transistors
Smaller is cheaper, faster, lower in power!
Revolutionary effects on society

[Moore65]
Electronics Magazine

Annual Sales (Estimated)

Power Density

Power density grew faster than cooling capacity
Hard to keep transistor junctions at safe temperature
What happens when junctions heat up?
Leakage rises rapidly → more power, potential thermal runaway
Carrier mobility drops → slower devices, timing margin loss
Accelerated aging (electromigration, BTI) → reduced reliability
Primary thermal sources in processors
Dynamic switching power (C·V²·f)
Leakage power (subthreshold, gate, junction)
Short-circuit power during transitions + clock/IO fabric

Courtesy, Intel

Not Enough Cooling

Overclocking: 9.1 GHz Record

Result: power density topped off

2023-2025 Power Density (Estimated)

Power density = power / die area (W/cm^2).

Chip	Year	Power Basis	Die Area	Power Density
Intel Core i9-14900K	2023	125 W PBP	257 mm^2	48.6 W/cm^2
AMD Ryzen 9 9950X	2024	170 W TDP	2x70.6 mm^2 (CCD)	120.4 W/cm^2
Apple M4	2024	9 W TDP	~130 mm^2 (est.)	6.9 W/cm^2 (est.)

AMD area is CCD-only (I/O die excluded). Apple M4 die size estimated from 28B transistors and TSMC N3E density (216 MTr/mm^2).

Sources: Intel 14900K AMD 9950X Apple M4 TDP M4 transistors TSMC N3E density

Frequency (Intel)

Power Dissipation (Intel)

How Small Is a 32nm Memory Cell?

Source: Kuhn, Intel

The Old Era of Scaling

It has served us well for >30 years

Courtesy, Mark Bohr, Intel

The New Era of Scaling

Avoiding the power wall requires a systematic approach from process technology through circuit design to micro-architecture to deliver products with power efficient performance

Courtesy, Mark Bohr, Intel

Huang’s Law?

Time to train AlexNet image classification deep neural network reduced by 500x (from 6 days to 18 mins) on GPU in last 5 years
Recent explosive growth in deep learning is enabled by HW innovation (along with availability of big data)
VLSI circuit and architecture techniques
More important as end of Moore’s law is approaching
Course covers fundamentals to enable VLSI circuit and architecture innovation

Bell’s Law: Birth of Computer Classes

Gordon Bell (1971; updated 2008): new computer class appears ~every decade
Trigger: cost/performance crosses a threshold + new applications emerge
Older classes persist but shift to infrastructure or niche roles
Typical sequence
Mainframe → Minicomputer → Workstation → PC → Laptop → Smartphone/Tablet → IoT/Edge

Sources: Bell, CACM 2008 Bell’s Law

Bell’s Law: Corollary – 100x Smaller

Each new class is ~100x smaller and cheaper over ~10 years
Form factors evolve: room → desk → lap → pocket → embedded
Shrinking size enables power efficiency and new usage patterns

Sources: Bell 2008 PDF Bell 2007 TR

Log-scale size trend for computer classes over time

Bell’s Law: Corollary – Ubiquity

As size/cost drop, device count rises
1 per enterprise → 1 per engineer → 1 per person → many per person
Today: multiple personal devices plus embedded sensors everywhere
IoT/edge compute is the newest class riding this trend

Mainframe-era computing system — Mainframe

Tiny embedded IoT device — IoT / Embedded

What does all this mean?

Chips are getting bigger and harder to design
Hierarchical design flow
Good design principles needed
Knowledge of fundamental design practices
Ability to develop innovative design techniques
This course is the first step
Prepares you for VLSI courses
Then you may be ready for creating your own start-up

Summary

We will focus this course on integrated circuits arising from semiconductor devices
Specifically digital circuits
We will include examples at each step of understanding
Our goal is to:
Get you familiar with the concepts
Internalize the concepts
Become proficient in using the concepts
Seeing how the concepts can be used for future work
You will need to keep up as the material moves fast!

Questions (before review)?

Interactive Apps

Electric Field

Visualize charge, field direction, and field strength.

Carrier Drift

See how carriers move under an applied electric field.

Bandgap

Explore band diagrams and how gaps affect carriers.

Review: Charge, Field, Voltage

Charge: a property of matter that creates electric forces; like charges repel and opposite charges attract.
Electric field: force per unit charge; it points in the direction a positive test charge would accelerate.
Voltage (electric potential): energy per unit charge; voltage differences drive current.

Review: Coulomb

Coulomb's law: electric force between charges scales as $ F = \frac{1}{4\pi\epsilon_0}\frac{q_1 q_2}{r^2} $, directed along the line between them.
Capacitance: how much charge a structure stores per volt, $ C = \frac{Q}{V} $.
Electric fields come from charges and shape how potential changes in space.

Band Energy and Bandgap

Band energy diagrams show allowed electron energy bands (valence and conduction) and the bandgap between them.
Energy in a solid refers to allowed electron energy levels in a periodic lattice.
Solving the Schrodinger equation in a lattice leads to allowed bands and forbidden energy ranges (bandgaps).

Materials and Ambipolar Transport

Conductors: overlapping bands or zero bandgap; carriers are abundant.
Insulators: large bandgap; very few carriers at room temperature.
Semiconductors: moderate bandgap; carrier concentration is tunable (doping, fields, light).
Ambipolar transport: current can include both electrons and holes in a semiconductor.
We control carrier concentrations by shifting energy levels (biasing, doping, or illumination).